Added KDE3 version of PikLab

git-svn-id: svn://anonsvn.kde.org/home/kde/branches/trinity/applications/piklab@1095639 283d02a7-25f6-0310-bc7c-ecb5cbfe19da

1 files changed, 279 insertions, 0 deletions

diff --git a/src/devices/pic/xml_data/18F1220.xml b/src/devices/pic/xml_data/18F1220.xml
new file mode 100644
index 0000000..e46f7f0
--- /dev/null
+++ b/src/devices/pic/xml_data/18F1220.xml
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--************************************************************************-->
+<!--* Copyright (C) 2005-2007 Nicolas Hadacek <[email protected]>            *-->
+<!--*                                                                      *-->
+<!--* This program is free software; you can redistribute it and/or modify *-->
+<!--* it under the terms of the GNU General Public License as published by *-->
+<!--* the Free Software Foundation; either version 2 of the License, or    *-->
+<!--* (at your option) any later version.                                  *-->
+<!--************************************************************************-->
+<device name="18F1220" document="010264" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x07E0" >
+
+<!--* Checksums ************************************************************-->
+  <checksums>
+    <checksum protected_blocks="0" bchecksum="0xF3EB" cchecksum="0xF341" />
+    <checksum protected_blocks="1" bchecksum="0xF5D6" cchecksum="0xF56D" />
+    <checksum protected_blocks="3" bchecksum="0x03D3" cchecksum="0x03BF" />
+  </checksums>
+
+<!--* Operating characteristics ********************************************-->
+  <frequency_range name="industrial" >
+    <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+  <frequency_range name="industrial" special="low_power" >
+    <frequency start="0" end="4"  vdd_min="2" vdd_max="5.5" />
+    <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" />
+  </frequency_range>
+  <frequency_range name="extended"   >
+    <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" />
+  </frequency_range>
+
+  <voltages name="vpp"            min="9"   max="13.25" nominal="13" />
+  <voltages name="vdd_prog"       min="4.5" max="5.5"   nominal="5"  />
+  <voltages name="vdd_prog_write" min="2"   max="5.5"   nominal="5"  />
+
+<!--* Memory ***************************************************************-->
+  <memory name="code"      start="0x000000" end="0x000FFF" word_write_align="4" word_erase_align="32" />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
+  <memory name="config"       start="0x300000" end="0x30000D" />
+  <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
+  <memory name="debug_vector" start="0x200028" end="0x200037" />
+
+<!--* Configuration bits ***************************************************-->
+  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0xCF" >
+    <mask name="FOSC"  value="0x0F" >
+      <value value="0x00" name="LP"           cname="_LP_OSC"     sdcc_cname="_OSC_LP" />
+      <value value="0x01" name="XT"           cname="_XT_OSC"     sdcc_cname="_OSC_XT" />
+      <value value="0x02" name="HS"           cname="_HS_OSC"     sdcc_cname="_OSC_HS" />
+      <value value="default" name="EXTRC_CLKOUT" cname="_RC_OSC"  sdcc_cname="_OSC_EXT_CLKOUT_on_RA6" />
+      <value value="0x04" name="EC_CLKOUT"    cname="_EC_OSC"     sdcc_cname="_OSC_EC_CLKOUT" />
+      <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"   sdcc_cname="_OSC_EC_PORT" />
+      <value value="0x06" name="H4"           cname="_HSPLL_OSC"  sdcc_cname="_OSC_HS_PLL" />
+      <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"   sdcc_cname="_OSC_EXT_Port_on_RA6" />
+      <value value="0x08" name="INTRC_IO"     cname="_INTIO2_OSC" sdcc_cname="_OSC_INT_Port_on_RA6_Port_on_RA7" />
+      <value value="0x09" name="INTRC_CLKOUT" cname="_INTIO1_OSC" sdcc_cname="_OSC_INT_CLKOUT_on_RA6_Port_on_RA7" />
+    </mask>
+    <mask name="FCMEN" value="0x40" >
+      <value value="0x00" name="Off" cname="_FSCM_OFF" sdcc_cname="_FCMEN_OFF" />
+      <value value="0x40" name="On"  cname="_FSCM_ON"  sdcc_cname="_FCMEN_ON" />
+    </mask>
+    <mask name="IESO"  value="0x80" >
+      <value value="0x00" name="Off" cname="_IESO_OFF" />
+      <value value="0x80" name="On"  cname="_IESO_ON"  />
+    </mask>
+  </config>
+
+  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
+    <mask name="PWRTE" value="0x01" >
+      <value value="0x00" name="On"  cname="_PWRT_ON"  sdcc_cname="_PUT_ON" />
+      <value value="0x01" name="Off" cname="_PWRT_OFF" sdcc_cname="_PUT_OFF" />
+    </mask>
+    <mask name="BODEN" value="0x02" >
+      <value value="0x00" name="Off" cname="_BOR_OFF" sdcc_cname="_BODEN_OFF" />
+      <value value="0x02" name="On"  cname="_BOR_ON"  sdcc_cname="_BODEN_ON" />
+    </mask>
+    <mask name="BORV"  value="0x0C" >
+      <value value="0x00" name="4.5" cname="_BORV_45" sdcc_cname="_BODENV_4_5V" />
+      <value value="0x04" name="4.2" cname="_BORV_42" sdcc_cname="_BODENV_4_2V" />
+      <value value="0x08" name="2.7" cname="_BORV_27" sdcc_cname="_BODENV_2_7V" />
+      <value value="0x0C" name="2.0" cname="_BORV_20" sdcc_cname="_BODENV_2_0V" />
+    </mask>
+  </config>
+
+  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" >
+    <mask name="WDT"   value="0x01" >
+      <value value="0x00" name="Off" cname="_WDT_OFF" sdcc_cname="_WDT_DISABLED_CONTROLLED" />
+      <value value="0x01" name="On"  cname="_WDT_ON"  sdcc_cname="_WDT_ON" />
+    </mask>
+    <mask name="WDTPS" value="0x1E" >
+      <value value="0x00" name="1:1"     cname="_WDTPS_1"   sdcc_cname="_WDTPS_1_1" />
+      <value value="0x02" name="1:2"     cname="_WDTPS_2"   sdcc_cname="_WDTPS_1_2" />
+      <value value="0x04" name="1:4"     cname="_WDTPS_4"   sdcc_cname="_WDTPS_1_4" />
+      <value value="0x06" name="1:8"     cname="_WDTPS_8"   sdcc_cname="_WDTPS_1_8" />
+      <value value="0x08" name="1:16"    cname="_WDTPS_16"  sdcc_cname="_WDTPS_1_16" />
+      <value value="0x0A" name="1:32"    cname="_WDTPS_32"  sdcc_cname="_WDTPS_1_32" />
+      <value value="0x0C" name="1:64"    cname="_WDTPS_64"  sdcc_cname="_WDTPS_1_64" />
+      <value value="0x0E" name="1:128"   cname="_WDTPS_128" sdcc_cname="_WDTPS_1_128" />
+      <value value="0x10" name="1:256"   cname="_WDTPS_256" sdcc_cname="_WDTPS_1_256" />
+      <value value="0x12" name="1:512"   cname="_WDTPS_512" sdcc_cname="_WDTPS_1_512" />
+      <value value="0x14" name="1:1024"  cname="_WDTPS_1K"  sdcc_cname="_WDTPS_1_1024" />
+      <value value="0x16" name="1:2048"  cname="_WDTPS_2K"  sdcc_cname="_WDTPS_1_2048" />
+      <value value="0x18" name="1:4096"  cname="_WDTPS_4K"  sdcc_cname="_WDTPS_1_4096" />
+      <value value="0x1A" name="1:8192"  cname="_WDTPS_8K"  sdcc_cname="_WDTPS_1_8192" />
+      <value value="0x1C" name="1:16384" cname="_WDTPS_16K" sdcc_cname="_WDTPS_1_16384" />
+      <value value="0x1E" name="1:32768" cname="_WDTPS_32K" sdcc_cname="_WDTPS_1_32768" />
+    </mask>
+  </config>
+
+  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x80" >
+    <mask name="MCLRE" value="0x80" >
+      <value value="0x00" name="Internal" cname="_MCLRE_OFF" sdcc_cname="_MCLRE_MCLR_disabled_RA5_input_en" />
+      <value value="0x80" name="External" cname="_MCLRE_ON"  sdcc_cname="_MCLRE_MCLR_enabled_RA5_input_dis" />
+    </mask>
+  </config>
+
+  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
+    <mask name="STVREN" value="0x01" >
+      <value value="0x00" name="Off" cname="_STVR_OFF" />
+      <value value="0x01" name="On"  cname="_STVR_ON"  />
+    </mask>
+    <mask name="LVP"    value="0x04" >
+      <value value="0x00" name="Off" cname="_LVP_OFF" />
+      <value value="0x04" name="On"  cname="_LVP_ON"  />
+    </mask>
+    <mask name="DEBUG"  value="0x80" >
+      <value value="0x00" name="On"  cname="_DEBUG_ON"  sdcc_cname="_BACKBUG_ON" />
+      <value value="0x80" name="Off" cname="_DEBUG_OFF" sdcc_cname="_BACKBUG_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+
+  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
+    <mask name="CP_0" value="0x01" >
+      <value value="0x00" name="0200:07FF" cname="_CP0_ON"  sdcc_cname="_CP_0_ON" />
+      <value value="0x01" name="Off"       cname="_CP0_OFF" sdcc_cname="_CP_0_OFF" />
+    </mask>
+    <mask name="CP_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_CP1_ON"  sdcc_cname="_CP_1_ON" />
+      <value value="0x02" name="Off"       cname="_CP1_OFF" sdcc_cname="_CP_1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
+    <mask name="CPB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
+      <value value="0x40" name="Off"       cname="_CPB_OFF" />
+    </mask>
+    <mask name="CPD" value="0x80" >
+      <value value="0x00" name="All" cname="_CPD_ON"  />
+      <value value="0x80" name="Off" cname="_CPD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
+    <mask name="WRT_0" value="0x01" >
+      <value value="0x00" name="0200:07FF" cname="_WRT0_ON"  sdcc_cname="_WRT_0_ON" />
+      <value value="0x01" name="Off"       cname="_WRT0_OFF" sdcc_cname="_WRT_0_OFF" />
+    </mask>
+    <mask name="WRT_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_WRT1_ON"  sdcc_cname="_WRT_1_ON" />
+      <value value="0x02" name="Off"       cname="_WRT1_OFF" sdcc_cname="_WRT_1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
+    <mask name="WRTC" value="0x20" >
+      <value value="0x00" name="All" cname="_WRTC_ON"  />
+      <value value="0x20" name="Off" cname="_WRTC_OFF" />
+    </mask>
+    <mask name="WRTB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
+      <value value="0x40" name="Off"       cname="_WRTB_OFF" />
+    </mask>
+    <mask name="WRTD" value="0x80" >
+      <value value="0x00" name="All" cname="_WRTD_ON"  />
+      <value value="0x80" name="Off" cname="_WRTD_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
+    <mask name="EBTR_0" value="0x01" >
+      <value value="0x00" name="0200:07FF" cname="_EBTR0_ON"  sdcc_cname="_EBTR_0_ON" />
+      <value value="0x01" name="Off"       cname="_EBTR0_OFF" sdcc_cname="_EBTR_0_OFF" />
+    </mask>
+    <mask name="EBTR_1" value="0x02" >
+      <value value="0x00" name="0800:0FFF" cname="_EBTR1_ON"  sdcc_cname="_EBTR_1_ON" />
+      <value value="0x02" name="Off"       cname="_EBTR1_OFF" sdcc_cname="_EBTR_1_OFF" />
+    </mask>
+  </config>
+
+  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
+    <mask name="EBTRB" value="0x40" >
+      <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
+      <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
+    </mask>
+  </config>
+
+<!--* Packages *************************************************************-->
+  <package types="pdip soic" nb_pins="18" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+  </package>
+
+  <package types="ssop"      nb_pins="20" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+  </package>
+
+  <package types="qfn"       nb_pins="28" >
+    <pin index="1"  name="" />
+    <pin index="2"  name="" />
+    <pin index="3"  name="" />
+    <pin index="4"  name="" />
+    <pin index="5"  name="" />
+    <pin index="6"  name="" />
+    <pin index="7"  name="" />
+    <pin index="8"  name="" />
+    <pin index="9"  name="" />
+    <pin index="10" name="" />
+    <pin index="11" name="" />
+    <pin index="12" name="" />
+    <pin index="13" name="" />
+    <pin index="14" name="" />
+    <pin index="15" name="" />
+    <pin index="16" name="" />
+    <pin index="17" name="" />
+    <pin index="18" name="" />
+    <pin index="19" name="" />
+    <pin index="20" name="" />
+    <pin index="21" name="" />
+    <pin index="22" name="" />
+    <pin index="23" name="" />
+    <pin index="24" name="" />
+    <pin index="25" name="" />
+    <pin index="26" name="" />
+    <pin index="27" name="" />
+    <pin index="28" name="" />
+  </package>
+
+</device>